1. Field of the Invention
The present invention relates generally to wiring structures for semiconductor memory devices and manufacturing method therefor and, more particularly, to "twisted wiring pair" for the signal line for semiconductor memory devices and manufacturing method therefor. The invention has particular utility in the field of folded bit line type of dynamic random access memory (DRAM).
2. Description of Background Art
Since the most preferable effect can be obtained when the present invention is applied to a dynamic random access memory, a description is made of the dynamic random access type in the following.
A dynamic random access memory has been already well known. FIG. 1 is a block diagram showing one of examples of the whole structure of such a conventional dynamic random access memory (which is hereinafter referred to as a DRAM).
Referring to FIG. 1, the DRAM comprises a memory cell array 41 comprising a plurality of memory cells serving as a memory portion, a row decoder 42 connected to an address buffer selecting its address, a column decoder 43 and an input/output interface portion comprising a sense amplifier connected to an input/output circuit. Each of the plurality of memory cells serving as the memory portion is connected to an intersection point between one of word lines connected to the row decoder 42 and one of bit lines arranged to the column decoder 43, which are constituted in a matrix fashion, to constitute the memory cell array 41. When a row address signal and a column address signal externally applied are received, the row decoder 42 and the column decoder 43 select a memory cell which is located at the intersection point between the selected word and bit lines. Data is written into the selected memory cell or data is read from that memory cell. Reading/writing of this data is indicated by a reading/writing control signal applied to a control circuit.
Data is stored in the N(=n.times.m)-bit memory cell array 41. Information relative to the memory cell in which reading/writing operation is performed is stored in row and column address buffers and the m-bit memory cell is coupled to the the sense amplifier by selecting a specific word line (one word line out of m word lines) by the row decoder 42. Then, by selecting specific bit line (one bit line out of m bit lines) by the column decoder 43, one of the sense amplifiers is coupled to the input/output circuit, whereby reading or writing operation is performed in accordance with a command of the control circuit.
FIG. 2 is an equivalent circuit diagram of a memory cell 40 of the DRAM which is shown to describe the writing/reading operation of the memory cell. Referring to FIG. 2, the memory cell 40 comprises a field effect transistor Q and a capacitor Cs. The gate electrode of the field effect transistor Q is connected to a word line 200 and the source/drain electrode connected to the capacitor Cs is connected to a bit line 300. In data writing, since the field effect type transistor Q becomes conductive when a predetermined voltage is applied to the word line 200, an electric charge applied to the bit line 300 is stored in the capacitor Cs. On the other hand, in data reading, since the field effect transistor Q becomes conductive when a predetermined voltage is applied to the word line 200, the electric charges stored in the capacitors Cs are taken out through the bit line 300.
In a semiconductor memory device, for example, the DRAM shown in FIG. 1, as a wiring method of signal lines transferring information from each memory cell to the sense amplifier, a bit line method (which is referred to as a folded bit line method) is known by which a pair of two bit lines are arranged from the sense amplifiers in the same direction. Referring to FIG. 3, a description is made of one of examples.
FIG. 3 is a schematic diagram showing the equivalent circuit structure of the conventional folded bit lines. As shown in FIG. 3, pairs of bit lines (BLO, BLO), BL1, BL1), . . . , (BLm, BLm) are arranged in the same direction from the sense amplifiers SA and the plurality of memory cells are coupled to each bit line. In this case, for example, if another wiring line such as A is arranged adjacent to one bit line BLO as a virtual wiring line, and The capacitance C between the wiring line A and the bit line BLO is large, noise is generated when a certain potential is applied to the wiring line A, whereby the potential of the bit line BL0 is changed. On the other hand, since the bit line BLO is spaced apart from the wiring line A, the potential of the wiring line A is less influential on it. As a result, when comparison is made between the potentials at the bit line BLO and BLO to detect a potential difference therebetween, malfunction of reversal of the result of the comparison between the potentials at the one and the other bit lines BLO and BLO is caused by the fact that the potential of the bit line BLO fluctuates.
In order to solve that problem, a twisted bit line method is proposed, by which two bit lines are intersected with each other a plurality of times as shown in FIG. 4. By way of example, a description is made of, the adjacent wiring line A as a virtual wiring line. The noise from the wiring line A uniformly influences the adjacent wiring lines (in this case, it is assumed that the number of intersecting times, its distances and the like are set so that a load capacitance C with both bit lines BL0 and BLO may be the same), that is, the bit lines BLO and BLO. As a result, when the potentials of the bit lines BL0 and BLO are compared to detect a potential difference therebetween erroneous operation is avoided because the influence of the noise can be neglected.
Various wiring pattern regarding the above mentioned twisted bit line method are proposed. For example, a wiring arrangement including a set of two bit lines intersected once is disclosed in Patrick W. Bosshart et al. "553-Transistor LISP Processor Chip" ISSCC '87 Digest of Technical papers P. 202. Japanese Patent Laying-Open Gazette No. 254489/1985 discloses a wiring arrangement including two bit lines intersected in the middle every other bit line pair. In addition, Japanese Patent Laying-Open Gazette No. 51096/1987 discloses a wiring arrangement including bit line pairs intersected with each other at even number positions and bit line pairs intersected with each other at odd number positions, both of which are alternately arranged. U.S. Pat. No. 3,942,164 discloses a wiring arrangement including a set of two signal lines leading from the sense amplifier in the same direction and intersected at a position of one half or one fourth of its distance. Furthermore, Japanese Patent Laying-Open Gazette No. 26895/1988 discloses a wiring arrangement including a pair of bit lines connected to the sense amplifier and having a plurality of intersecting points which do not coincide with those of adjacent pair of bit lines.
However, although various wiring methods in accordance with the twisted bit line method were proposed as described above, a wiring structure for implementing the method, that is, the planar arrangement and the cross-sectional structure of a wiring layer have not been proposed yet. Recently, a memory cell has progressively become more compact as a degree of integration of a memory has been enhanced. The space between signal lines such as bit lines connected to each memory cell has been also reduced. Consequently, as the signal line connected to each memory cell becomes minute, it becomes noticeable that in a semiconductor memory device such as the DRAM, an error of information transmission due to the noise from another wiring line, so-called erroneous operation, is liable to occur. Therefore, it is desired that a specific configuration and structure of the wiring layer for implementing the twisted bit line method be proposed, in which malfunction of information transmission can be controlled by uniformly distributing the noise from another adjacent wiring line to a pair of signal lines.